1. Field of the Invention
Generally, the present disclosure relates to the manufacture of sophisticated semiconductor devices, and, more specifically, to various methods that involve the use of pattern matching techniques to identify and resolve potential non-double-patterning-compliant (NDPC) patterns or layouts that are encountered when using double patterning techniques to manufacture integrated circuit products.
2. Description of the Related Art
Integrated circuit products, or ICs, are generally created by patterning several layers of material so as to define the various devices and components, e.g., transistors, resistors, capacitors, etc., that are used to make the product. Generally, the process starts with the design of the integrated circuit using an electronic design automation (EDA) tool that allows a designer to interactively position and connect various components of the circuit. This design, in turn, is generated into a circuit layout by the electronic design automation tool. The circuit layout, also known simply as a layout, contains the physical locations and dimensions of the circuit's components, interconnections and various layers. The components, interconnections and various layers of the circuit form the features of the integrated circuit. As noted above, the integrated circuit design is eventually fabricated by transferring the circuit layout to a semiconductor substrate in a series of layers that collectively will form the features that constitute the devices that make up the components of the integrated circuit. However, before the layout can be fabricated, a validation process of the layout must take place.
Design Rule Checking (DRC) is the area of electronic design automation (EDA) that determines whether the physical layout of a particular chip layout satisfies a series of recommended parameters called design rules. Design rule checking is a major step during physical verification of the chip design. Design rules are a series of parameters provided by semiconductor manufacturers that enable the chip designer to verify the correctness of a product layout and the mask sets (reticle) used in manufacturing the product. Advanced processes and products may involve the use of more restrictive design rules in an effort to improve product yield.
Design rules may be specific to a particular semiconductor manufacturing process and/or product. In general, a design rule set specifies certain geometric and connectivity restrictions between features of the layout to ensure sufficient margins to account for variability in semiconductor manufacturing processes and to ensure that the circuits work as intended. Typically, there are several basic types of design rules that semiconductor manufacturers employ. The first are single layer rules, such as, for example, width rules, spacing rules and pitch rules. A width rule specifies the smallest allowable width of any shape in the design, i.e., the width of a metal line or a gate electrode structure. A spacing rule specifies the minimum distance between two adjacent features, like the spacing between two adjacent metal lines. Spacing rules can vary depending upon the nature of the relationship between the two adjacent features, e.g., corner-to-corner spacing, tip-to-side spacing, side-to-side spacing, tip-to-tip spacing, etc. The magnitude of the space allowed by these various spacing rules will likely not be the same in all situations, e.g., the allowable tip-to-tip spacing may be different from the allowable side-to-side spacing. Additionally, the magnitude of the allowed spacing will likely be tighter (smaller) for more advanced products and processes as compared to older product generations. These single layer rules will exist for each layer of a semiconductor product, with the lowest levels typically having the tightest or most restrictive design rules and the highest metal layers on the product typically having larger, less restrictive design rules. There is also what is known as two layer design rules. A two layer design rule specifies a relationship that must exist between features on two separate layers of the product. For example, an enclosure design rule might specify that an object of one type, such as a contact or via, must be covered, with some additional margin of error, by a metal layer. There are many other design rules that are not discussed herein.
Typically, the design validation process is handled by a verification tool, which processes a circuit layout and verifies that the layout adheres to a set of specified design rules. One such verification tool is sometimes referred to as a design rule checker. Often times the design rule checker is implemented as a stand-alone software program, such as Cadence Assura®DRC, or as a part of an electronic design automation tool, such as Cadence Virtuoso®. The design rule checker examines a layout for violations of a set of specified design rules. The layout is usually received by the design rule checker in the form of a file that digitally represents the layout of the circuit. Current formats for layout files include, but are not limited to, GDS II and OASIS. When a design rule checker observes a circuit feature within the layout that violates a particular design rule, the violation is flagged by the design rule checker. Examples of how this flagged violation can be brought to the designer's attention include, but are not limited to, marking the violation directly in a resulting output layout file or graphically bringing attention to the violation within the electronic design automation tool.
Photolithography is one of the basic processes used in manufacturing integrated circuit products. At a very high level, photolithography involves: (1) forming a layer of light or radiation-sensitive material, such as a photoresist material, above a layer of material or a substrate; (2) selectively exposing the radiation-sensitive material to a light generated by a light source (such as a DUV or EUV source) to transfer a pattern defined by a mask or reticle (interchangeable terms as used herein) to the radiation-sensitive material; and (3) developing the exposed layer of radiation-sensitive material to define a patterned mask layer. Various process operations, such as etching or ion implantation processes, may then be performed on the underlying layer of material or substrate through the patterned mask layer.
Of course, the ultimate goal in integrated circuit fabrication is to faithfully reproduce the final circuit layout (design) on the integrated circuit product. Historically, the pitches employed in integrated circuit products were large enough such that a desired pattern could be formed using a single patterned photoresist masking layer. However, in recent years, device dimensions and pitches have been reduced in size to the point where existing photolithography tools, e.g., 193 nm wavelength photolithography tools, cannot form a single patterned mask layer with all of the features of the overall target pattern. Accordingly, device designers have resorted to techniques that involve performing multiple exposures to define a single target pattern in a layer of material. One such technique is generally referred to as double patterning or double patterning technology (DPT). In general, double patterning is an exposure method that involves splitting (i.e., dividing or separating) a dense overall target circuit pattern into two separate, less-dense patterns. The simplified, less-dense patterns are then printed separately utilizing two separate masks (where one of the masks is utilized to image one of the less-dense patterns, and the other mask is utilized to image the other less-dense pattern). Further, in some cases, the second pattern is printed in between the lines of the first pattern such that the imaged wafer has, for example, a feature pitch which is half that found on either of the two less-dense masks. This technique effectively enables the printing of even smaller features than would otherwise be possible using a single mask using existing photolithography tools. There are several double patterning techniques employed by semiconductor manufacturers.
One illustrative double patterning technique involves exposing the same layer of photoresist material to two separate exposure steps using two different reticles. After the second exposure, the double-exposed photoresist layer is then developed so as to define a patterned photoresist mask that may be used, for example, as an etch mask to transfer the pattern defined in the patterned photoresist mask to an underlying layer of material.
Another illustrative double patterning technique is more involved and generally involves creating the ultimate or desired target pattern in a hard mask material by performing two lithography and two etch processes—this process is sometimes referred to as an LELE (Litho-Etch-Litho-Etch) process. In an LELE double patterning process, a first photoresist layer is formed above a hard mask layer. Thereafter, the first photoresist layer is exposed during a first exposure process and subsequently developed to define a first patterned photoresist mask. Next, an etching process is performed through the first patterned photoresist mask on the hard mask layer to transfer the pattern in the first patterned photoresist mask to the hard mask layer. The first patterned photoresist mask is then removed from the now partially patterned hard mask layer. Next, a second photoresist layer is formed above the partially patterned hard mask layer. The second photoresist layer is then exposed during a second exposure process (using a different reticle) and subsequently developed to define a second patterned photoresist mask. An etching process is then performed through the second patterned photoresist mask on the partially patterned hard mask layer to transfer the pattern in the second patterned photoresist mask to the partially patterned hard mask layer. This latter etching process results in a final patterned hard mask layer having the desired target pattern. The second patterned photoresist mask is then removed. The final patterned hard mask layer may then be used to pattern an underlying layer of material.
To use double patterning techniques, an overall target pattern must be what is referred to as double-patterning-compliant. In general, this means that an overall target pattern is capable of being decomposed into two separate patterns that each may be printed in a single layer using existing photolithography tools. Layout designers sometime speak of such patterns with reference to “colors,” wherein the first mask will be represented in the EDA tool using a first color and the second mask will be represented in the EDA tool using a second, different color. To the extent a layout is non-double-patterning-complaint, it is sometimes stated to present a “coloring conflict” between the two masks. An overall target pattern may have many regions or areas that cannot be printed because the features in those regions are spaced too closely to one another for existing photolithography tools to be able to print such closely spaced features as individual features. To the extent an overall target pattern has an even number of such features, such a pattern is sometimes referred to as an “even cycle” pattern, while an overall target pattern that has an odd number of such features is sometimes referred to as an “odd cycle” pattern. Even cycle patterns can be formed using double patterning techniques, while odd cycle patterns cannot be formed using double patterning techniques.
If a layout cannot be separated or “decomposed” into two masks, the problem can be addressed by changing the circuit layout. The circuit layout is usually changed manually by a designer reviewing the output from design rule checking software. Changing a circuit layout is time-consuming and expensive because a designer aims to minimize the total volume of a circuit layout and a change to a portion of a circuit layout often affects structures in other layers or regions of the circuit layout. A designer must evaluate many alternate fixes before determining the best solution. Additionally, some fixes do not necessarily resolve certain odd cycle situations. Therefore, improved methods for efficiently resolving double patterning constraint violations are desired.
FIGS. 1A-1D depict a very simplistic circuit layout that will be helpful in understanding the concepts mentioned above. FIG. 1A depicts a very simplistic circuit layout 11. The circuit layout 11 is comprised of line-type features 13 and 15A-15C. The “X” in FIGS. 1A-1D indicates where a design rule violation exists, i.e., the features are positioned too closely to one another. Thus, the circuit layout 11 in FIG. 1A cannot be formed using a single patterned photoresist mask. The initial task is to determine whether or not the circuit layout 11 can be formed using double patterning techniques.
To that end, FIG. 1B depicts one possible arrangement 11A or so-called “coloring” in which the circuit layout 11 can be “decomposed” into two separate mask layers. Layout designers sometime speak of such patterns with reference to “colors,” wherein the first mask will be represented in the EDA tool using a first color and the second mask will be represented in the EDA tool using a second, different color. To the extent a layout is non-double-patterning-complaint, it is sometimes stated to present a “coloring conflict” between the two masks. Layout designers also use the phrase “coloring solution” in describing various situations. For example, a potential non-double-patterning-compliant (NDPC) pattern may be referred to as a pattern that is perceived to have “no coloring solution.” In FIG. 1B, one mask is depicted in dashed lines while the other mask is depicted in solid lines. More specifically, a first mask is comprised of only the feature 13, while a second mask is comprised of the three features 15A-15C. While the first mask does not violate any design rules, the second mask still violates the spacing design rules as indicated by the two “Xs” in FIG. 1B. Thus, the possible arrangement 11A, i.e., the first possible coloring solution, is not double-patterning-compliant.
FIG. 1C depicts another possible arrangement 11B, i.e., another possible coloring solution, in which the circuit layout 11 can be “decomposed” into two separate mask layers. In FIG. 1C, one mask is depicted in dashed lines while the other mask is depicted in solid lines. More specifically, a first mask is comprised of the features 13 and 15B, while a second mask is comprised of the features 15A and 15C. While the second mask does not violate any design rules, the first mask still violates the spacing design rules as indicated by the “X” in FIG. 1C between the features 13 and 15B. Thus, the possible arrangement 11B, i.e., the second coloring solution, is not double-patterning-compliant.
From the foregoing, it is clear that the circuit layout 11 is a layout that is an impossible-to-decompose (ITD) pattern that cannot be formed using double patterning techniques. Accordingly, the designer must modify or “fix” the circuit layout 11 such that it may be formed using double patterning techniques. To that end, FIG. 1D depicts an illustrative fixed arrangement 11F that is double-patterning-compliant. In this example, the fix involves reducing the axial length of the feature 15B in the region 17. This results in a new feature 15B1 that is spaced farther away from the side surface of the feature 13. This change effectively eliminates the design rule violation depicted in FIG. 1C. More specifically, as shown in FIG. 1D, a first mask is comprised of the features 13 and 15B1, while a second mask is comprised of the features 15A and 15C. Neither the first nor second mask violates any design rules, as indicated by the absence of any “Xs” in FIG. 1D. Thus, the fixed arrangement 11F is double-patterning-compliant.
FIG. 2 depicts one illustrative example of a prior art electronic design automation process that is performed for checking a layout to insure that the layout is both design-rule-compliant and double-patterning-compliant. As shown in FIG. 2, the software 10 is comprised of several functional modules that perform various activities. In general, an initial drawn circuit layout 12, in digital form, is subjected to analysis by the software 10 to determine whether or not the layout 12 is both design-rule-compliant (DRC) and double-patterning-compliant (DPT), as reflected in block 14. To the extent the initial layout 12 passes both the design rule checking and double patterning checking (PASS), the initial layout 12 is declared to be both design-rule-compliant and double-patterning-compliant, as indicated in block 16. To the extent that the initial layout 12 fails the design rule and/or double patterning checking (FAIL) in block 14, the entire initial layout 12 is subjected to decomposition in block 18. At that point, the initial layout 12 is decomposed in block 20 to produce a new post-decomposition layout 12A. The new post-decomposition layout 12A is then subjected to design rule checking and double patterning checking in block 22. To the extent the new post-decomposition layout 12A passes both the design rule checking and double patterning checking in block 22 (PASS), the new post-decomposition layout 12A is declared to be both design-rule-compliant and double-patterning-compliant, as indicated in block 24. To the extent that the new post-decomposition layout 12A fails the design rule and/or double patterning checking (FAIL) in block 22, the new post-decomposition layout 12A is determined to have one or more potential non-double-patterning-compliant (NDPC) patterns or layouts that must be fixed to eliminate the situations that are causing the new post-decomposition layout 12A to fail the design rule and double patterning checks, as indicated in block 26. Such fixes may involve adjusting the spacing, position and/or location of one or more features of the NDPC patterns. Determining which fixes to make is a very complex problem as movement or re-sizing of one feature on an integrated circuit product may necessitate changing the location, position or size of another feature. Moreover, there are typically several possible fixes to a particular problem. Thus, the designer must evaluate which solution is best for the particular problem at issue. As a result of fixing the NDPC patterns in the new post-decomposition layout 12A, a modified circuit layout is produced, as indicated in block 28. This modified circuit layout is then processed through the software 10 beginning with design rule checking and double patterning checking in block 14, as indicated in FIG. 2. This process is then repeated until a final circuit layout is determined to be both design-rule-compliant and double-patterning-compliant.
Design rule checking and double patterning checking are very computationally intense tasks. Usually, design rule checks will be run on each sub-section of a product to minimize the number of errors that are detected at the top level. If run on a single CPU, customers may have to wait up to a week to get the result of a design rule check for modern integrated circuit designs. Most design companies need to or would like to reduce the time involved in performing design rule checking/double patterning checking operations, i.e., it is desirable to achieve reasonable cycle times since design rule checking/double patterning checking operations will likely be performed several times prior to producing a final circuit layout that is both design-rule and double-patterning-compliant. With today's processing power, full-chip design rule checking/double patterning checking operations may be performed more quickly. Nevertheless, reducing the time involved in validating and correcting errors in a product layer such that the final product layout is design-rule-compliant and double-patterning-compliant is a highly desirable goal.
State-of-the-art software for checking for double patterning compliance identifies potential non-double-patterning-compliant (NDPC) patterns through the use of automated decomposition algorithms. Importantly, such software identifies so-called coloring conflicts, but only after the circuit layout has been decomposed. This basic strategy may present several problems. First, since there is, by definition, no coloring solution for a potential non-double-patterning-compliant (NDPC) pattern, the state-of-the-art software uses an arbitrary coloring or masking arrangement as a starting point to decompose the rest of the circuit layout. Such an approach tends to result in a sub-optimal decomposed layout. Second, when using the state-of-the-art methodology, identifying and generating error markers for the features that cause coloring conflicts, i.e., the features that cause the layout to be non-decomposition-friendly, increases the run-time of the software tool, thereby slowing down the design process. Third, the state-of-the-art systems do not provide any localized guidance for fixing the coloring conflict. Unlike traditional rule-based checks and violations, layouts that are determined by the software to be potential non-double-patterning-compliant (NDPC) patterns are typically caused by the interactions among a chain of several features. Even with the error markers provided by the state-of-the-art systems, it is extremely difficult for a layout designer to readily understand the information presented and to devise a timely proposed solution.
The present disclosure is directed to various methods that involve use of pattern matching techniques to identify and resolve potential non-double-patterning-compliant (NDPC) patterns that are encountered when using double patterning techniques to manufacture integrated circuit products which may solve or at least reduce one or more of the problems identified above.